1. Field of the Invention
The present invention relates to a wiring layout method of an integrated circuit.
2. Background of the Related Art
A multilayer wiring process has been carried out for achieving a high integration density in semiconductor integrated circuits. Too much large or small value of wiring area ratio in each wiring layer causes deteriorating of the flatness of inter-layered insulator and lowering of the yield rate or reliability. Forming dummy wiring in empty areas of wiring guarantees its wiring area ratio to be higher than the allowable minimum value.
FIG. 10A shows a case where a layout design process has been carried out for an inverter 10, a NAND gate 11, a flip-flop 12, a NOR gate 13 and a multiplying circuit 14. Conventionally, after the layout design process has been finished, a checking window Q1 of, for example, 7×7 μm is set for checking whether or not the wiring area ratio is more than its allowable maximum value, and it is then shifted to the checking window Q2 in the shown arrowed-direction, repeating the same procedure.
However, when the setting location of the checking window Q1 is slightly changed to be as shown in FIG. 10B, it is occurred, for example, that an error is detected by the checking window Q2 of FIG. 10B but it is not detected by the checking window Q2 of FIG. 10A, causing a checking miss. As a result, it takes place that the flatness of inter-layered insulator gets worse, thereby lowering the reliability of semiconductor devices.